Electronic Design Automation Software: The Picks and Shovel Play of AI
Cadence Design Systems
Executive Summary
Cadence Design System (CDNS) is an Electronic Design Automation (EDA) software provider that is mission-critical in the design of advanced digital semiconductor chips. It exists in a Duopoly with Synopsys, with Siemens (Previously aka Mentor Graphics). I find there is evidence to suggest that there is a favourable shift in dynamics between the EDA providers and their customers, signifying it's strengthening moat.
Investment Thesis – The Widening Moat
My thesis for CDNS is simple:
(1) EDA faces further industry tailwinds for more advanced chip technology. The current 3nm chips that we now have on the iPhones are something that was developed 2-3 years ago. The ongoing advancement paths are 2nm chips and 3D Die-stacking technology.
Design cost for chips get exponentially higher as complexity rises, requiring better software and verification tools. As reported by IBD, the design cost for a 2nm chips is US$725 mm, of which majority is related to EDA.
![Chip Design and Manufacturing Cost under Different Process Nodes: Data Source from IBS [2].](https://substackcdn.com/image/fetch/$s_!ahvL!,f_auto,q_auto:good,fl_progressive:steep/https%3A%2F%2Fsubstack-post-media.s3.amazonaws.com%2Fpublic%2Fimages%2Fb714c9bf-522d-41ba-b03d-49adf5ed7f1d_640x334.png "Chip Design and Manufacturing Cost under Different Process Nodes: Data Source from IBS [2].")
Chip design costs rise exponentially. On the other hand, Die-stacking is meant to surpass physical limitations. By stacking multiple dies on top of each other, we can unlock multiple times of processing power. However, this technology does not come free of problems. Our current single-layer GPUs already overheat when computer games – what more when we have multiple layers of Die. Physical Verification/Chip Simulation is mission-critical to ensure proper heat management of the chips. This further increases the EDA industry's bargaining power. This why Synopsys wants to acquire Ansys .
(2) As wafer prices continue to rise , failure in the chip manufacturing process becomes increasingly costly. Wafer prices continue to climb as the size of transistors gets even smaller – Thus, the opportunity cost of producing inferior chip designs rises, increasing the need for the chip design to be perfect before proceeding to the manufacturing facility.
Conclusion: As the two trends above begin to surface, I find that the power dynamics between CDNS and its customers shifting in favour of CDNS. Previously, after GFC, CDNS pursued long-term contracts with its customers to improve revenue visibility and cash flow stability. However, one of the statements made by one of CDNS’s executives surprised me.
Our focus is really on growing the annual value of that backlog. So I mean, like a three-year software contract worth $10 million a year, we'll add $30 million to backlog into RPO and a two-year contract worth $12 million a year will add $24 million to backlog in RPO…..Now if it's a choice between those two options with one customer, we'll typically take the $12 million a year because $12 million a year is better than $10 million a year”
What this fundamentally means is that CDNS or at least its CDNS’s management, with a high degree of certainty, has now achieved dominance over its customers. Its products are so important and integral to its customer’s operations that their pricing power over them is secured and has even strengthened. This also explains why revenue growth for CDNS has also begun accelerating in recent years.
Industry Overview
Before I dive into the thesis, since this is my first coverage of CDNS, I would like to briefly introduce EDA, the EDA industry, and its main players in the field.
EDA
EDA is the bread and butter of the chip design process. It is the software that enables chip design engineers to create designs. Chip design is a difficult process that requires engineers to design and verify integrated circuits to ensure that the chip performs as expected.
IC Specifications/Requirements (Step 1):
Figure out what the chip needs to do and how fast it needs to do it.
Determine how much power it should use and how much it should cost.
This helps decide the basic needs of the chip without getting into the technical details of how it will be made.
Logic/Circuit Design (Step 2):
Use pre-made building blocks like memories and processors to put together the main functions of the chip.
Break down these functions into detailed circuit elements with the help of software.
Test the design using computer simulations to make sure it works as intended.
At this stage, start thinking about how the chip will be created.
Physical Design (Step 3):
Create a layout for the chip, deciding where different parts will be placed.
Analyze the layout for potential issues like delays or congestion.
Place individual transistors and connect them with wires to make the chip work.
Check and re-check the design at each step to make sure it aligns with the plan.
Physical Verification (Step 4):
Check for any physical effects that might occur during manufacturing, like resistance or signal interference.
Make rules to ensure the design can handle these effects.
Think about how the chip will be placed on the silicon wafer during manufacturing.
Signoff (Step 5):
Final checks on critical aspects like timing, power use, and signal quality.
Make sure nothing will cause problems during manufacturing or affect the chip's performance.
Once everything looks good, send the design for actual manufacturing.
So, in a nutshell, it's like planning (Step 1), designing the details (Step 2), deciding how it physically looks (Step 3), making sure it can handle manufacturing (Step 4), and then giving it the final OK before making it (Step 5). So it is mainly Chip Designing and Verification of Design.
As transistors go from micrometres to nanometres, ICs now hold billions of transistors and other components, requiring a specific layout to deliver its specified performance.
The EDA Industry, its players, and its customers
During the nascence of the EDA industry, there were many small individual companies – they all focused on small portions of the chip design process.
Over time, some players began to merge and acquire other small players to integrate their software into a full-flow design system. Companies that have a full suite of integrated software tools manage to stand out to design customers as it reduces the difficulty of shifting design models around and simplifies software purchases. Greater cash flow enabled more R&D for better software, which further enhanced their competitive positioning.
Today, there are 4 giants left – Synopsys, Cadence Design Systems, Siemens (aka Mentor Graphics), and Ansys Systems. If the current acquisition of Ansys by Synopsys goes through – Another one bites the dust - there would be a duopoly with a small third player.
Fabless Chip Designers, like NVIDIA and AMD, and Integrated Device Manufacturers (IDMs) all need EDA to keep designing the next generation of ICs to remain relevant. The future of these companies is mainly dependent on their ability to create more advanced chips and accelerate their time-to-market for new advanced chips.
Low Cyclicality of EDA
Taking the revenue of the top 20 listed Semiconductor companies and comparing it to the EDA industry revenue, we can observe that EDA does not have the cyclicality of semiconductors. This is because EDA is a part of the R&D cost for these companies.
Consistent Semiconductor R&D
Looking at the same top 20 companies, we can see that R&D expenses have never fallen over the past 10 years. R&D is essential to the future of the semiconductor industry.
Company Overview
As one of the two hegemons of the EDA world, CDNS currently has an estimated 30% market share in the EDA space. It has had an incredible transformation since the early 2000s with the business model going through a complete overhaul after GFC in 2008.
Business Model Shift
Prior to the GFC, most software was sold on an indefinite basis, meaning that after a single payment, customers could use the software indefinitely. This business model would ultimately spark major price cuts among EDA providers as companies competed to maximise the sales.
However, as all tech companies go, they gradually shifted to a subscription service model when the then-relatively unknown Lip Bu-Tan took over. He pushed to seamlessly integrate all their prior acquisitions into a single coherent eco-system and constantly spoke with their customers to receive feedback from them. And the numbers speak for themselves.
Financial Metrics
Gross Margins
Over the past 10 years, CDNS’s GPM has steadily maintained above 80% and has inched slowly towards 90%. This results from their proportion of revenue attributable to service revenue falling as compared to the software subscription revenue. Like any other software business, CDNS has stunning GPMs.
Operating Margins
CDNS’s execution is what stands out for me. CDNS has successfully managed to lock in its customers and continuously up-sell its newly acquired software. The number of companies buying from them hasn’t really changed, but the revenue growth has completely outstripped Sales & Marketing and General & Administrative expenses, which I take to be substantial evidence of their excellent execution.
As ex CDNS CFO Geoff Ribar once mentioned in their Q4 2014 earnings call:
I think as we said in our Q3 earning call, we are winning new business with top customers. And these are the customers that you want us to be winning designs with. And so to win and keep these designs, we have to invest in technology as we mentioned in our last call and outstanding customer technical support. As the ramp these customers, it’s important for us to keep these customers by making this investment and also to hopefully proliferate going forward.
Their success in achieving lower operating margins was engineered since 2014. Their strategy was just to win over the top customers, make sure they were very satisfied with the tools and constantly upsell the subscriptions with their new acquired software. This strategy worked because their number of customers doesn't increase drastically and manpower requirements remains relatively constant because the sales relationship only needs to be maintained. Thus, we can see a substantially decrease in Marketing and Sales expenses as a proportion of total income.
Overall, this company has executed its business strategy to perfection that’s why it can continue to be priced at such a premium compared to other software companies.
Furthermore, I find that its sustained high ROIC is a testament to the incredible moat it has.
Valuation
These are some of my own estimates for CDNS.
With the advent of AI, autonomous driving, AR/VR technology and so many more technologies, I find that CDNS's revenue will maintain a high-teens yoy growth as its importance rises. An ever-growing need for better chips necessitates tremendous R&D expenditure which fuels the EDA industry.
I believe that CDNS deserves a fair valuation using Forward 26 P/E (GAAP) of 50x slightly above its implied 26 P/E (GAAP) of 44.2x, because of its widening moat.
For CDNS, i do not use non-GAAP numbers. Currently, on SA's valuation page, you can see that the displayed Forward P/E on CDNS summary page is on a non-GAAP basis, which excludes SBC, acquired intangibles, acquisition, integration-related costs and many other items. I find that this is misleading as I find that since CDNS is a serial acquirer, these items are relevant to its core operations which acquiring business and integrating them into it network.
Risks
Currently, CDNS has two risks:
Geographical Risk: Because of the US-China Semiconductor war, US has banned the export of Gate-All-Around Field Effect Transistor (GAAFET) technology which is necessary for the design of sub-3nm designs. As a result, CDNS exports an inferior export-approved version of their EDA software to China that does not support GAAFET. This has also led to China calling for more domestic EDA providers to upgrade their offerings. The local players only have an estimated 12% domestic market share, while CDNS, SNPS and Siemens have a 77% market dominance. For now, domestic players seem to lag, but CDNS could eventually lose their dominance there. China is about 15-17% of their total revenues. I would estimate that they would gradually lose their dominance within China in about 3 years, which is roughly when China’s Empryean Technology will get 5nm EDA. I am a bit more conservative on China’s ability to each 5nm EDA, because these leaps often take years, especially with all the US restrictions on them.
Technological Obsolescence: As with all technology companies, there may exist a new trend of open-source EDA software that might eventually surface. However, I find that CDNS and SNPS play in the high-end design space. If open-source were to grow, it would only be for the low-end older chip market. Nevertheless, there is always a risk.
Open source EDA: There are attempts of making new free EDA software online. However, these software will never be able to produce viable designs for the high-end chips. This is because all top EDA players need to receive the Process Design Kit (PDK) from manufacturers such as TSMC to ensure compatibility between digital design and actual machinery specs. These specs are not open to the publics and are given out on a limited basis. Thus, I don't consider this a risk.
Conclusion
CDNS is the ideal semiconductor play because regardless of who produces the best chips, everyone always spends on R&D. After all, nobody can afford not to. The EDA industry is a rational industry with CDNS and Synopsys seeming to exist in a tacit truce, raising prices on both sides.
A Forward 26 P/E (GAAP) of 50x valuation is a high number for almost any normal tech company. But CDNS is not a normal company and thus cannot be valued like a normal tech company. It sits at the very forefront of human technology. As long as we need semiconductors, CDNS will thrive.